Typically, in a computer system, communication between a central processing unit such as a microprocessor (MPU) and a peripheral device occurs in connection with data transfer cycles. In interfacing an MPU and a peripheral device timing is an important consideration. Examples of two critical timing parameters are read and write access times. These are the times needed for internal address decoders to locate the correct byte in memory. To accommodate these access times, it is well known to make wait states part of the nominal transfer cycle. Also, a handshake protocol between the MPU and the peripheral device is commonly employed to insert additional wait states into the transfer cycle in order to ensure a particular peripheral device has available to it the needed access time. For this purpose, most MPUs include a READY input which when deactivated serves to add wait states to a transfer cycle up to some predetermined maximum number of consecutive states.
Other timing parameters are, of course, associated with the transfer of data between an MPU and peripheral during a transfer cycle. Historically, however, these other timing parameters have not required special consideration in large part because they were typically not of the same order of magnitude as the nominal time period of the transfer cycle. Therefore, special precautions to prevent violation of these parameters has not been necessary.
Special situations exist, however, where a peripheral device is characterized by a timing parameter that is of the same order of magnitude as the transfer cycle. For example, in the video subsystem of an IBM Personal System/2.TM. model 50, 60 or 80, a digital-to-analog converter (DAC) contains a color look-up table (CLUT) which allows eight (8) bit pixel valves to be translated into six (6) bit red, green and blue components before the digital-to-analog conversion takes place, allowing up to 256 colors out of a possible 256K colors to be displayed. The CLUT can be written to and read from the MPU by its performing write and read commands to certain input/output (I/O) addresses. One of the timing parameters of the video DAC places a limitation on how soon the leading edge of a read or write strobe can occur after the trailing edge of a previous read or write strobe. This timing parameter is related to the asynchronous relationship between the pixel stream and the system clock. In order to ensure the pixel stream is not disrupted during a read or write command, the timing parameter requires up to six (6) pixel or dot clocks (e.g., 480 nanoseconds) as a minimum separation between the trailing edge of one signal and the leading edge of the next.
With increasingly faster microprocessors, instruction and transfer cycle times have decreased dramatically. With these increasing microprocessor speeds, timing parameters of peripheral devices such as that of the aforementioned video DAC are violated unless software delays are inserted between consecutive transfer cycles. These software delays, however, may not continue to be effective as machine speeds continue to increase and operating systems become more sophisticated.